The present invention pertains generally to the field of computer systems. More particularly, the present invention relates to the field of computer system bus architecture.
A bus architecture of a computer system conveys much of the information and signals involved in the computer system""s operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In many hardware applications, such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate.
In many computer system architectures of today, the Peripheral Component Interconnect (PCI) bus is commonly used to achieve high bandwidth connectivity between peripheral devices and processors. Although the PCI bus has a high bandwidth, its full potential cannot be achieved by incorporating only a single PCI bus within a computer system. For instance, if too many electrical loads (e.g., devices) are placed on a PCI bus, it may cease to function correctly. As another example, the devices that populate a particular PCI bus may not co-exist together well. A master that requires a lot of bus time in order to achieve good performance must share the bus with other masters. Demands for bus time by these other masters may degrade the performance of the PCI bus.
These problems could be solved by adding one or more additional PCI buses into the system and re-distributing the device population. A system designer can add another PCI bus into the system by using a PCI-to-PCI bridge device. The PCI-to-PCI bridge provides a bridge from one PCI bus to another, but it only places one electrical load on its host PCI bus. The new PCI bus can then support a number of additional devices and/or PCI expansion connectors. In order to further increase the number of additional PCI devices, a system designer could include more than one PCI-to-PCI bridges in the system.
However, one problem associated with the addition of multiple PCI-to-PCI bridges is that only a limited number of PCI interfaces can be implemented on a single integrated circuit. Another problem is that circuit boards implementing the PCI bus require a very high trace density to accommodate the trace implementation, as well as all the electromagnetic interference (EMI) and radio frequency interference (RFI) shieldings. The addition of multiple PCI-to-PCI bridges in the system would require an even higher trace density, and would unnecessarily increase the manufacturing costs of the circuit boards.
Therefore, what is needed is a novel system and method for providing high data bandwidths between devices of a computer system. What is yet further needed is a system and method for reducing the interconnect cost of a parallel bus with minimal impact to the data rate.
The present invention provides a low pin count, moderate speed serial data bus with a variable width for the transfer of data between devices of a computer system. According to one embodiment of the present invention, the serial data bus may be selectively configured to be a 1-bit, 4-bit, 8-bit or 16-bit wide bus. Data (including bus commands and addresses) carried by wider parallel buses are serialized into bus-width-sized blocks, which are then transferred by the serial data bus at a high speed.
One feature of the present invention is that the pin count requirement is low. In one embodiment, a bi-directional data transfer protocol implemented with only four pins is used for controlling the data transfer mechanisms. Particularly, data transfers are controlled by two signals PACKET# and READY#. In one embodiment, the bus master initiates the data transfer by asserting the PACKET# signal. Then, the bus master transmits bus commands, addresses or event codes across the variable width data bus to the slave. When data is ready to be read, or when empty buffers are available, the slave asserts the READY# signal. Burst mode read and write requests are indicated by the bus master by keeping the PACKET# signal asserted through the cycle preceding the cycle that transferred the last bit of the data byte. A third signal REQ/GNT# is used to implement a single wire bus arbitration protocol for performing bus arbitration. A fourth signal required by the present embodiment is the bus clock signal CLK.
Another significant feature of the present invention is that the host and companion interfaces of the serial data bus can have non-matching widths. To allow for host and companion interfaces with non-matching widths, an initialization protocol is used to establish the effective width of the data bus at power-on reset. Particularly, after power-on reset, the effective width of the data bus is set to 1 bit. In this 1 bit mode, the host interface determines the width of the companion interface, and then sets the width of the data bus to the smaller of the host and companion interfaces.
Other significant features and advantages of the present invention not specifically mentioned here will become apparent in the detailed description below.